Pulse generating system



Sept- 18, 1952 l L. s. BENSKY ET AL PULSE GENERATING SYSTEM Original Filed April 20, 1955 3 Shams-Sheet 1 Mik ` Afro/ENE? Sept. 18, 1962 L. s. BENSKY ETAL 3,054,958

PULSE GENERATING SYSTEM original Filed April 20. 1955 3 Sheets-Sheet 2 Sept. 18, 1962 s. BENSKY ET AL 3,054,958

PULSE GENERATING SYSTEM Original Filed April 20, 1955 5 Sheets-Sheet 5 United States Patent Office 3,054,958 Patented Sept. 18, 1962 $54,958 PULSE GENERATENG SYSTEM Loweil S. Bensky, Levittown, Pa., and David L. Nettleton and Arthur D. Beard, Haddonfield, NJ., assignors to Radio Corporation of America, a corporation of Delaware Griginal application Apr. 2t?, 1955, Ser. No. 502,647, now Patent No. 2,926,338, dated Feb. 23, 1960. Divided and this application Oct. 12, 1956. Ser. No. 615,593

Claims. (Cl. 328-56) This invention relates to a pulse generating circuit of a type useful, for example, in a system for storing data magnetically.

This application is a division of our copending application entitled Method of and System for Storing Data Magnetically, Serial No. 502,647, filed April 20, 1955, now Patent No. 2,926,338, and assigned to the same assignee as the present invention.

Many of the present data (information) handling systems employ data storage units. This stored data is generally handled by some type of computer. A program control unit of the computer controls the flow of information into, within, and out of the computer. The stored information may be in the form of characters, each cornprising a group of coded binary signals.

In many of these systems, it is desirable to store information for various periods of time and yet have the information readily available for reading or alteration. Storing the characters of information on a magnetic drum, or on a continuous strip of material which is rotatable at a high rate of speed or on other cycle storage media is a solution to this problem. The desired information can then be located and read off into the computer or other information handling device as needed.

It is accordingly desirable to store, that is, pack, the information as tightly as possible on such cyclic media in order to store a maximum amount of information within a given area. It is also desirable to cycle the drum, or other storage member, as rapidly as possible to achieve a minimum access time to any desired information location. Access time may be defined as the time interval between the instant certain data is called for and the instant at which that data is derived from the storage unit. These two requirements are not always compatible with either the storage unit itself or the data handling system itself. Thus, many data handling systems are only capable of handling the characters of information at fixed time rates. As both the amount of information stored Within a given area, and the speed of rotation of a drum, for example, are increased, the time interval between successive characters on the drum is decreased until a point is reached at which the maximum operating speed of the information handling system is exceeded.

To achieve compatibility between the operating speed of the information handling system and that of the cyclic data storage unit itself, the latter unit must be either cycled at a lower rate thereby increasing access time, or the packing density of the information decreased. Generally, it is not desirable to increase the access time. Accordingly, it is apparent that the packing density of information on a magnetic drum must be decreased thereby causing the drum to be inherently wasteful of storage area. This same philosophy is applicable to other cyclic data storage systems and mediums.

Accordingly, it is an object of this invention to provide an improved system, which system is capable of storing a greater amount of information Within a given storage medium.

Another object of this invention is to provide an improved system for storing information, which system provides a shorter access time to the information.

Another object of this invention is to provide a method making more efcient use of a cyclical storage medium.

A more general object of the invention is to provide a new and improved circuit for producing pulses.

Another object of the invention is to provide a System for deriving timing pulses from the pulses recorded on the synchronizing track of a magnetic drum.

Another object of the present invention is to provide for a computer having a drum containing interlaced stored information, a timing pulse system responsive to the synchronizing pulses recorded on the drum synchronizing track, which permits access to any line of information on the drum within one drum revolution and which, thereafter, reads (or writes) information on the drum in interlace fashion.

The invention, in its broader aspects, includes a coincidence circuit to which recurrent input pulses spaced time intervals T from one another are applied. These input pulses may be the synchronizing pulses recorded on the synchronizing track of the drum. The coincidence circuit is enabled so that the recurrent input pulses pass through the input circuit. A pulse circuit means coupled to the coincidence circuit produces a group of n output pulses, during the interval T following a given input pulse, in response to this given input pulse. After the production of the group of n output pulses and during said interval T following the given input pulse, the coincidence circuit is disabled and a second input pulse derived from the group of pulses is applied to the pulse producing circuit.

In accordance With a preferred embodiment of the invention, synchronizing pulses derived from the timing track of a magnetic drum storage device are applied to a timing pulse generator. This timing pulse generator functions to control the basic timing rate of an information handling system, which includes the drum, and generate two series of four timing pulses each, for a total of eight. Each sequence of eight timing pulses is generated upon the occurrence of every other synchronizing pulse from the magnetic drum timing track. With the information handling system under the control of this basic timing cycle which occurs with each alternate drum line, the timing pulse generator allows alternate lines to be read from the drum. The drum may then be cycled at whatever rate the information handling device can properly respond. At the same time, the drum may be packed with information solidly. In this manner, substantially twice as much information may be packed on the drum and used in a highly eiiicient manner as would be possible without this arrangement.

In accordance with another feature of this invention, a particular drum line may be selected without loss of access time by suppressing the second group of four timing pulses and generating a group of four timing pulses in response to very drurn line. In this manner, each drum line in succession may be counted until a selected drum line occurs.

The novel features of this invention as well as the invention itself both as to its organization and method of operation will best be understood from the following description when read in connection with the accompanying drawings, in which like reference numerals refer to like parts, in which:

FIGURE 1 is a block diagram showing a manner in which this invention may be used in conjunction with a typical information handling system;

FIGURE 2 is a block diagram of the timing pulse generator employed in FIGURE 1, in accordance with a preferred embodiment of this invention.

FIGURE 3 illustrates the time distribution of the timing pulses produced in accordance with the embodiment of this invention as shown in FIGURE 2.

FIGURE 4 is a block diagram of an alternative embodiment of the timing pulse generator shown in FIGURE 2.

The present invention is embodied in a system which is more fully described in a copending application entitled Information Handling System, Serial Number 478,021, filed December 28, 1954, by the applicant, Lowell S. Bensky. It may be noted that several of the components bear similar designations and the same reference numerals as the simil-ar components in the drawing and specification of the said Bensky application. The said Bensky application describes an information handling system in detail including the various operations, among which is the technique of using alternate drum lines to pack a greater amount of information upon a program drum in the system. The present invention is also described in a copending application entitled Information Handling Devices, Serial Number 478,022, tiled December 28, 1954, now Patent No. 2,877,446, by Sublette et al. The said Sublette application describes a method and system for reading information from tape, drum or other storage media into a high speed type memory. The present application shows the information handling system described in the said applications in an abbreviated form, including only so much as to provide a clear and ready understanding of the present invention.

The date upon which the computer acts may be stored in Ia static memory which, by way of example, may comprise two banks designated respectively, the left high speed memory 15 and the right high speed memory 16 (see FIG. l). Hereafter, the abbreviation HSM is employed for high speed memory. Each memory bank may be of the type employing magnetic magnetic cores and may be assumed to include read-out and read-in circuits which may be respectively actuated by pulses or high levels. On the occurrence of -a pulse at the appropriate circuit, the memory is placed in condition and thus receives information applied thereto at its information-in circuits or supplies information at its informationout circuit. The information-in r out is in the form of binary digits of information or bits each represented by the pulses (or voltage level) on one of several leads. Seven bits in this instance may be stored at each address and written-in or read-out in parallel. However, one of these seven bits is a parity bit, and is ignored in describing the present invention.

As will appear more fully hereinafter, a series of timing (that is, clock) pulses are provided in cycles of approximately twenty microseconds. It is assumed that the read-in and read-out circuits, although actuated, are further actuated internally only upon the occurrence of a timing pulse designated TPS. Information may be received or fed out of the memory throughout the period from timing pulse TPS to timing pulse TP6.

A program drum PD is supplied in a known manner with a timing track and a reset track. Program drum PD is preferably a magnetic drum continuously rotated. As the drum rotates, pulses are generated in reading heads (or other transducing means) from the timing track in synchronism with lines of information written on the drum in the form of binary numbers magnetically stored in twelve data channels. With the occurrence of every other pulse from the timing track, the timing pulse generator TPG generates a series of eight timing pulses designated as TPI to TPS, respectively. The particular manner of generation of timing pulses will be described morev fully in conjunction with the explanation of FIG. 2 and especially the manner whereby every alternate pulse from the timing track is suppressed. This latter :feature provides a unique method of line interlace, whereby greater compression of the information on the drum may be obtained. 'Ihe reset track on the program drum PD provides a single iiducial pulse from which the lines on the drum are counted.

Six of the data channels on the program drum PD are read by six left reading heads and amplifiers 51 and the other six data channels are read by six right reading heads and amplifiers 52. A gate 150 receives the pulse from the reset track of the program drum PD and applies it to the reset terminal R of the drum counter DC. The gates herein are all logical and gates and are indicated by rectangles, with the priming leads directed toward the rectangle and the output leaving the rectangle. The gate 150 is a two-input gate. In addition to the input from the reset track, another input is indicated, which for the purpose of the present application may be considered always high and the gate therefore always open.

The drum counter DC may be a counter of nine stages. Each of the counters and registers herein may be flip-flop counters or registers. The trigger terminal T of the drum` counter DC receives the output o-f an or" circuit. This or circuit is provided with two inputs. One, the first timing pulse TPI and the other the fifth timing pulse TPS. In the drawing in this application, as in the Bensky application, a special convention is adopted for the showing of an or circuit. According to this convention, the inputs to the or circuit are indicated by arrowheads converging to a point which is the center of a small circle. A single line from the center of this circuit indicates the output.

A program counter PC is provided having nine ilipilop stages. The outputs of the program counter PC are applied to inputs of an equality circuit 5t). Other inputs o-f the equality circuit Si) are from the flip-flop stages of the `drum 'counter DC. A flip-liop is a circuit having two stable states, that is, conditions, and two input terminals, one of which is designated as set and the other of which is designated as reset. The flip-tlop may assume the set condition by application of a high level or pulse on the set input terminal S or the reset condition .by application of a high level or pulse on a reset terminal R. Two outputs are associated with the output circuit which are given Boolean tags of one and zero If the flipaop is in its set condition, that is set, the one output voltage is high and the zero output voltage is low. Unless otherwise indicated, the outputs `from flip-flops are taken from the one terminal. If the flip-flop is reset (that is, in its reset condition) the one terminal is low and the zero terminal is high. A -iiip-flop may also be provided with a trigger terminal T. Application of a pulse to the trigger terminal T causes the flip-flop to assume the other condition from the one it was 4in when the pulse was applied. Counters are formed from flip-flops in a known manner.

In this application, multiple leads are indicated by dotted lines. Each lead of these multiple leads carrie-s, as the machine operates, a binary digit of information aving only two possible voltage levels, one high and one low. These voltage levels may be either a constant voltage or in the form of pulses. Therefore, the lines themselves are sometimes designated as bits (binary digits of information). The equality circuit S0 may comprise a group of and gates. 'I'here are two and gates for each corresponding stage of the two counters, one and gate being -for each pair of corresponding leads. The outputs olf each pair of and gates corresponding to each of the stages, respectively, of the counters are supplied (in pairs) through or circuits to a single and gate (not shown). Accordingly, the equality circuit 50 has a pulse output, if, and only if, the binary numlber in the program counter PC is the same as the binary number in the drum counter DC.

The Aoutput of the equality circuit is connected to the set input vS of a single drum line match flip-flop F125. The reset input R of the drum line match flip-flop F is received by what is herein broadly termed a program control unit PCU. Note that this PCU does not correpond exactly with the PCU of FIG. 1 of the said Bensky application. The program control unit may include an arithmetic unit and controls of the flow of data between .the high speed memories and 16 and itself. The arithmetic unit includes an adder. The program control unit can thus control the -flow oi' data to perform logical operations as addition, subtraction, multiplication, etc., on the data in the high speed memory. Further, the pro- -gram control unit FCU is connected to the set input of the program counter FC and functions to supply the address of the information desired on the magnetic drum PD. As is indicated by the dotted line, this address is supplied on parallel channels to the program counter. In addition, the program control unit supplies a reset pulse to the reset input R of the program counter. It should be noted that the drum address may also be set into the program counter by a keyboard arrangement and the program counter reset by a D.C. switching voltage. Likewise, the drum line match flip-Hop F125 may be reset in the same manner as the program counter PC.

The timing pulse generator receives the one output of the drum line match flip-flop F125 as do the program control unit FCU and a gate 242. The function of this input to the timing pulse generator from the drum line match iiip-flop F125 is to control whether the timing pulse generator TPG generates (l) a sequence of eight timing pulses in response to each alternate pulse received from the timing track 0f the program drum PD or (2) a sequence comprising only the first four of these timing pulses in response to every succeeding synchronizing pulse received from the timing track. A second input to the gate 242 is completed by timing pulse channel TF2. The output of the lgate 242 is connected to prime the left and right reading heads and amplifiers 51 and 52.

In operation, a particular program `drurn address may be set up in the program counter PC. With the drum line match ip-ilop F125 reset, gate 242 twill prevent the reading heads 51 and 52 from reading `any information from the drum PD. After the reset track has reset the dr-um counter DC, successive synchronizing pulses from the timing track causes the timing pulse generator TPG to generate sequences of four timing pulses TF1 to T P4 inclusive. Each TF1 advances the drum counter DC `by one. Upon reaching equal-ity with the drum address set up in the program counter PC, the drum line match flip-flop F125 is set, thereby creating `a high level output to the timing pulse -generator TPG and gate 242. This high level allows the reading heads 51 and 52 to read the magnetic drum PD every TF2. In addition, the mode of operation of the timing pulse generator is shifted to generate eight timing pulses (TF1 to TPS inclusive) in response to every alternate synchronizing pulse. Accordingly, since the reading heads are actuated only during TF2, alternate drum lines are read, whereas every drum `line is searched before the proper count is attained. The reading of only alternate drum lines allows a lfaster drum rotation, thereby decreasing access time over that of a drum wherein every line is read.

Since a specific function of the computing system is not the subject of the .present invention, any further explanation as to the specific functions of the computer, as such, are deemed superfluous. The specific circuitry of a preferred embodiment of a timing pulse generator TPG which may be employed to accomplish this invention is shown in FIG. 2. Referring now to FIG. 2, the input to Ithe timing pulse generator TPG from timing track of the program drum FD is connected through a coincidence :gate 235 to a group of `serially connected delay lines D1, D2, and D3. Delay lines are well known in the art and may, for example, be comprised of a plurality of LC sections.

The output from the drum timing track (actually from the coincidence gate 235) and the outputs of each of the delay line sections D1, D2, and D3 are coupled to corresponding ones of the first of two inputs of a first group of coincidence gates 201, 202, 203, and 204, respectively. In addition, these outputs lfrom the timing track and the several delay lines D1, D2, and D3 are also coupled to corresponding ones of the first of two inputs of a second group of coincidence gates 205, 206, 207, and 208. The output of each coincidence gate, in both the first and second groups of gates, -are indicated by arrows. The output from the first group of coincidence gates (and gates) are herein labeled TF1, TF2, TF3, and TF4, and that of the second group of and gates TF5, TF6, TF7, and TPS. These eight parallel channels supply sequential timing pulses to a utilization device, herein illustrated by the control unit FCU of the information handling device shown in FIGURE l.

The output of the last-in-tirne and gate 204 of the first group of and gates 201, 202, 203, and 204, that is, timing pulse T P4, is connected to the first input of a two input and gate 237. The output of and gate 237 is connected to the set input of a commutating flip-flop F201. The second input to and gate 237 may be provided by a high or low level voltage, by way of illustration, from the program control unit PCU of the information handling system as illustrated in FIGURE l. This second input to the and gate 237, as before, may be designated as a priming input. ln a similar manner, the output of the last-in-time and gate 20S of the second group of and gates 205, 206, 207, and 20S, that is, timing pulse TPS, is coupled to the reset input of the commutating iiip-flop F201. The zero, that is, reset, output of the commutating flip-iiop F201 is connected to the second input of each one of the first group of and gates 201, 202, 203, and 204, respectively, and to the second input of and gate 235. Because of its mode of operation, the second input of each and gate is designated herein as the priming input. The set (that is, one) output of the commutating flip-flop F201 is connected to the second (priming) input of each one of the second group of and gates 205, 206, 207, and 208. The output of and gate 237 is connected through a delay line D4 to the common input of the first delay line D1 and the corresponding N and gates 201 and 205 of the first and second groups of and gates, respectively.

This timing pulse generator constitutes an improvement over a pulse generator described in a copending application of Martin Kaplan for Pulse Generator, Serial No. 502,572, filed April 20, 1955, now U.S. Patent 2,860,243.

The operation of the timing pulse generator may best be understood by referring to FIGURE 2, and to FIG- URE 3 wherein the time sequence of the timing pulses TF1 through TF8, inclusive, is illustrated. Let us assume that the pulses herein illustrated as from the drum timing track produce a synchronizing, that is, clock, pulse every ten microseconds, and that the delay line sections D1, D2, and D3 each provide a delay of two microseconds. Under these conditions, the several pulses introduced from the several points on the delay lines D1, D2, and D3 to the several gates at two microsecond intervals. Assume, for the moment, that the voltage level on the input to and gates 237 herein shown to be from the drum line match ip-flop F is high. With the commutating flip-fiop F201 in a reset condition, that is, the reset output high, and therefore the priming inputs to the first group of and gates 201, 202, 203, and 204, inclusive, along with and77 gate 235 are energized. Application of the synchronizing pulses from the timing track will now appear at each of the corresponding pairs of and gates i 201-205, 202-206, 203-207 and 204-208 comprising the first and second groups of and gates, respectively, in sequence. The presence of the priming input to the first group of and gates 201 through 204, inclusive, allows the pulses to pass as they arrive, thereby generating TF1, TF2, TF3, and TF4 at two microsecond intervals.

Upon the occurrence of the TF4 pulse, and gate 237 passes an impulse to the commutating ilip-flop F201, and through delay line D4 to the input of the chain of delay lines, thereby setting ilip-op F201 to prime the inputs of each of the second group of and gates 205, 206, 207, and 208, inclusive. The first group of and gates 201, 202, 203, and 204, inclusive, as well as and gate 235, now have a low level priming input and thus do not pass any signals. Accordingly, the TP4 pulse, passing through the delay line D4, generates a second series of timing pulses TPS, TP6, TP7, and TPS in sequence. Upon the advent of the eighth timing pulse TPS, the commutating flip-flop F201 is reset, thereby priming the first group of and gates 201, 202, 203, and 204, inclusive, simultaneously with and7 gate 235, preparatory to the receipt of the next synchronizing pulse from the drum, which latter pulse now starts the sequence over again.

In another mode of operation, the priming input to and gate 237, herein illustrated as from the program control unit PCU, is low. The T P4 timing pulses do not pass to set the commutating Hip-flop 201. Accordingly, the timing pulse generator generates only the lirst four timing pulses TF1 to TF4, inclusive. A particular usage of this alternative mode of operation has been briefly set forth above, as in the search operation for a particular drum address.

The pulse generator of FIG. 2 may be employed in an information handling system utilizing a cyclic storage device as now set forth in greater detail with reference to FIG. 1. The rst synchronizing pulse from the timing track (distinguish from the first timing pulse TP1), following the reset (that is, index or iiducial) pulse from the reset track of the magnetic drum PD, is passed to the timing pulse generator TPG to become the first timing pulse TPI. The ducial (that is, index pulse) from the magnetic drum PD passing from the gate 150 resets the drum counter DC. (Subsequently, the remaining timing pulses through TPS, TP6, TP7, and TPS are varied in the manner described above in response to this tirst synchronizing pulse from the timing track.) With the occunrence of the rst set of timing pulses TP1 through TP4 after the index pulse (assuming that the input to the timing pulse generator from the drum line match ip-op F1251 is low), the count of the drum counter DC is advanced by one pulse. The iirst timing pulse TPI is applied to the first trigger terminal T (of the lowest order stage) of the drum counter DC. The count of the drum counter DC is now advanced in like manner for each drum line, each of which parallels each record pulse which passes under the drum heads.

Assume, for example, that the program counter PC had previously been set by the program control unit PCU to the desired number (that is, count) of the drum line desired to be read-out. The comparison circuit 50 compares each bit of information previously entered in the previous flip-flop of the program counter PC with the corresponding ones of the drum counter DC. The equality circuit 50 may be a group of and gates and or gates, arranged to have a high input, if and only if the two binary numbers, one from the drum counter DC and the other from the program counter PC, are equal.

Accordingly, when the count previously set in the program counter PC corresponds to that in the drum counter DC, the equality circuit sets the drum line match flip-flop F125. The ip-flop F125 thereby primes and gate 237 (FIG. 2) of the timing pulse generator as well as gate 242 and the program control unit. The primed reading heads and amplifiers 51, 52 now read-out or read-in the six bits of information from each of the two information channels on the program drum PD. The particular functioning and disposition of this information to or from the high speed memories and 16 is controlled by the program control unit.

Gate 237 (FIG. 2) now being primed, passes the fourth timing pulse TP4 to set the commutating ilip-llop F201. Setting iiip-op F201 in turn primes the second group of and gates 205, 206, 207, and 208 and blocks the succeeding synchronizing pulse from the program drum PD. Timing pulses TPS, TP6, TP7, and TPS result from that fourth timing pulse TP4 which is fed back to the input of the delay lines D1, D2, D3 through delay line D4. The eighth timing pulse is now applied to reset the commutating flip-flop F201 to reopen the first group of gates 201 through 204 and gate 235, and close the second group of gates 205, 206, 207, and 203. One drum record line has meanwhile passed the drum heads. Accordingly, with the last pulse occurring when the alternate lines passes the drum heads, from the timing track of the program drum PD, another first timing pulse TPI is passed by gate 201 and a cycle of the timing pulses recurs unless a different action occurs to stop the passage of these pulses. Therefore, as every other drum line passes the reading heads a new cycle of eight timing pulses occurs. If the second timing pulse TP2 is used to gate the reading amplifier, each alternate drum line is read.

It should be noted at this point that either the pulse generator disclosed in the Kaplan application or any other pulse generator which produces sequences of timing pulses in response to alternate synchronizing pulses may be used. It is further desirable that this pulse generator be capable of generating a shorter sequence of pulses in response to every synchronizing pulse to provide for searching for a given line. In this manner the pulse generator is always at TP1 at the start of the read-in or read-out, once the proper drum line is found. One advantage of this feature is that the program control unit now keeps track or count of the amount of information read-in or out, and the maintainence of this record is readily achieved by counting each starting point TP1 in the cycle of timing pulses. Regardless, however, of the pulse generator used, the result is the same. Thus, the drum counter DC keeps the proper count of every record line arriving under the reading heads, and each alternate drum line is read in accordance with a computer cycle lwhich is one-half that of which the information is available from the magnetic drum. The proper count is achieved by the drum counter DC because of the inputs on both the TPI and TP5 timing pulses. Further, the rapidity of access from any drum line is not reduced by virtue of the slower read-out, since any `drum line is still accessible in not more than one revolution of the drum. Thus, the timing pulse generator arrangement provides means whereby when a complete cycle of timing pulses is generated only certain drum lines start each cycle, and intermediate drum lines between these certain (in this instance, alternate) lines for the current cycle are ignored. A novel manner of reducing the read-out or cycle rate and still maintaining the density of packing of information, and yet providing the same rapidity of access is thus provided.

In an alternative embodiment, the principles of this invention may be extended to provide selectively varying numbers of output pulses on parallel channels. In this alternative embodiment, as shown in FIGURE 4, synchronizing pulses are coupled, as in FIG. 2, through an and gate 235 to a group of delay lines D1, D2, and D3. The output of and gate 23'5 and of each of the delay lines D1, D2, and D3 is applied to the inputs of each of a Itirst, second, and third group of and gates (four and gates are assumed to comprise each group as in FIG. 2). In place of the flip-flop F201 (FIG. 2) a counting circuit C500 is employed. The l output of each of the 0, 1 and 2 stages of the counting circuit is utilized to prime the iirst, second, and third groups of and gates, respectively. The 1 output from the zero stage of the counter C500 is also coupled to the priming input of and gate 235. The last-in-time pulses, TF4 and TPS, from each of the irst and second groups of and gates, respectively, is coupled to the count input of the counting circuit C500. These timing pulses TP4 and TPS pass through and gates 237 which are primed by the drum line match flip-flop F (FIG. l). In addition to being coupled to the count input of the 9 counting circuit C500, the timing pulses TP4 and TPS are also coupled through delay line D4 to the input of the delay lines D1, D2, and D3. TP12 is coupled to the reset input of the counting circuit C500.

The operation of the generator of FIG. 4 is similar to that described with reference to FIG. 2. If the drum line match ip-ilop F125 is low, only the iirst four timing pulses TPI to TP4, inclusive, are produced. If, on the other hand, the drum line match flip-ilop F125 is high (indicating the desired drum line which is utilized in conjunction with the system of FIG. l), and gates 237 are opened and a sequence of twelve timing pulses are generated in response to every third synchronizing pulse. TF4 and TPS provide the necessary input to the delay lines D1, D2, and D3 during the interval when the input synchronizing pulses are blocked by and gate 235. Upon the advent of the twelfth timing pulse T1312, the counter C500 is reset and the third synchronizing pulse is passed to start the cycle again. Thus, by using a small number of delay lines, timing pulses can be generated in accordance with any desired multiple of synchronizing pulses. By the interlace principle, information may be read from alternate, every third, or whatever multiple of line is desired.

There has been hereinabove described a novel method and system whereby the requirement of a minimum access time to a maximum amount of information stored in a cyclic storage medium is obtained. This compatibility between requirements is obtained in a unique manner requiring a minimum amount of equipment. Further, a timing pulse generator is disclosed, which provide sequences of timing pulses on parallel channels in response to multiples of synchronizing pulses. The invention provides a means of and method for matching the information input and output rates of a cyclic storage medium (for example, a magnetic drum) to the output and input rates, respectively, of the utilization equipment.

What is claimed is:

l. A signal generating circuit for generating pulses on parallel output channels in response to input pulses cornprising, in combination, a iirst coincidence gate to which said input pulses are directly applied, a second coincidence gate, a third coincidence gate, a delay means through which the output pulses of said iirst coincidence gate are applied to said second and said third coincidence gates, a multivibrator responsive to the outputs of said second and third coincidence gates to provide two different steady state outputs, said irst and said second coincidence gates both being responsive to a given output of said multivibrator, and said third coincidence gate being responsive to the other said multivibrator output, whereby alternate input pulses are blocked, the output of said second coincidence gate being connected to the input of said second and third coincidence gates, thereby providing substitute pulses for said blocked pulses.

2. A signal generating circuit for generating pulses on parallel output channels in response to alternate input impulses comprising, in combination, a first coincidence gate responsive to said input impulses, second and third coincidence gates, both said second and said third coincidence gates being responsive to the output of said first coincidence gate, coincidence means coupled to the output of said second coincidence gate, means to selectively prime said coincidence means, a multivibrator having a iirst input and a seond input, said lirst multivibrator input being coupled to the output of said coincidence means, said second multivibrator input being coupled to the output of said third coincidence gate, said first and said second coincidence gates being responsive to a given steady state output from said multivibrator, and said third coincidence gate being responsive to a different steady state output from said multivibrator, and a delay line having an input and an output, the output of said coincidence means being also coupled to the input of said delay line, said second and said third coincidence gates l@ being responsive to the output of said delay line, whereby said second and third coincidence gates will selectively pass multiples of said impulses as determined by said control means.

3. A signal generating circuit comprising, in combination, a pulse source for generating sequential pulses, a coincidence gate coupled to the output of said pulse source, a plurality of serially connected delay means coupled to the output of said coincidence gate, a iirst plurality of coincidence means, each one of said iirst plurality of coincidence means being responsive to the output of a given one of said delay means, a second plurality of coincidence means, each corresponding one respectively ot said second plurality of coincidence means being responsive to said given output of a different one of said delay means, coupling means responsive to a control signal for coupling the output of one of said second plurality of coincidence means to the input of said plurality of serially connected delay means, and means responsive to said coupling means for priming said coincidence gate and said rst plurality of coincidence means in the absence of said control signal, and for priming said second plurality of coincidence means in the presence of said control signal and said output of said one of said second plurality of coincidence means whereby said signal generating circuit selectively provides successive iterations of signals responsive to multiples of said sequential pulses.

4. A signal generating circuit as claimed in claim 3 wherein said means for priming comprises a bistable multivibrator.

5. A signal generating circuit of the type claimed in claim 4 wherein said bistable multivibrator has a set input, a reset input, and a pair of outputs responsive respectively to said set and reset inputs and wherein the output of one of said first plurality of coincidence means is connected to the set input of said multivibrator and to the input to said plurality of serially connected delay means, the output of one of said second plurality of coincidence means is connected to the reset input of said bistable multivibrator, and wherein said coincidence gate and each one of said jrirst and said second plurality of coincidence means have a priming input, the priming inputs of said first coincidence means and each one of said iirst plurality of coincidence means being connected to the reset output of said bistable multivibrator, the priming input to each one of said second plurality of coincidence means being connected to the set output of said bistable multivibrator.

6. In a pulse generating system, a coincidence circuit to which recurrent input pulses spaced time intervals T from one another are applied; means coupled to said coincidence circuit for enabling said coincidence circuit, whereby said pulses pass through said circuit; pulse circuit means connected to receive the output of said coincidence circuit for producing a group of n output pulses, during the interval T following a given input pulse, in response to said input pulse; and means including a feedback circuit of said pulse circuit means for disabling said coincidence circuit to prevent the same from passing a recurrent pulse to said pulse circuit means and for applying an input pulse to said pulse circuit means both during the time interval T following said given input pulses and after said group of n output pulses.

7. In a pulse generating system, a coincidence circuit to which recurrent pulses spaced time intervals T from one another are applied; circuit means coupled to said coincidence circuit for enabling the same, whereby said pulses pass through said coincidence circuit; pulse generating means connected to receive the output of said coincidence circuit for generating a group of output pulses, during the interval T, in response to each input pulse; and means including said circuit means responsive to a pulse in said group of output pulses for disabling said coincidence circuit for preventing a recurrent pulse from 1l, passing through said coincidence circuit to said pulse generating means and for applying an input pulse to said pulse generating means for causing the latter to generate a second group of output pulses.

8. in a pulse generating system, a coincidence circuit to which recurrent pulses spaced time intervals T from one another are applied; circuit means coupled to said coincidence circuit for applying an enabling voltage thereto, whereby said pulses pass through said coincidence circuit; pulse generating means connected to receive the output of said coincidence circuit for producing a group of n output pulses in response to each input pulse; means including said circuit means responsive to the last occurring of said group of output pulses for applying a disabling voltage to said coincidence circuit to prevent the same from passing the next occurring recurrent pulse; means including a delay means for applying said last occurring of said group of output pulses directly to said pulse generating circuit for causing the latter to generate a second group of n output pulses; and means including said circuit means, responsive to the last occurring of said second group of output pulses, for reapplying an enabling voltage to said coincidence circuit.

9. In the system as set forth in claim 8, saidpulse generating means comprising delay line means, and output terminals spaced along the length of said delay line means.

10. In the system as set forth in claim l8, said circuit means comprising a bistable multivibrator.

References Cited in the le of this patent UNITED STATES PATENTS OTHER REFERENCES Electronics, vol. 25, Issue 10, pp. 15o-157, October 1952. 

